At last the whole circuit is simulated and shows that the desired functions and performances are achieved . The layout is designed with virtuoso layout editor, then the DRC and LVS are performed.

• 最后,对整体电路进行了联合仿真,模拟结果表明该电路完成了设计功能、达到了预先制定的设计指标,进而采用Cadence 下的Virtuoso Layout Editor 工具进行了版图设计,并进行DRC 和LVS 的版图验证。