Based on the design of instruction pre-fetch FIFO for an embedded RISC processor, a SDRAM power model has been presented to optimizing the FIFO design.

• 本文从一个嵌入式RISC处理器的指令FIFO设计出发，提出了SDRAM的功耗模型，基于该功耗模型，提出了最优化的指令FIFO设计。