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- central memory control 中央存储器控制器
- In the case of active SLE,CCR7+ central memory T c ells may interact with dendritic cells,and induce differentiation of syngeneic CD4+T to Th2 cells. 活动期SLE患者外周血CCR7+中央型记忆性T细胞可与树突细胞相互作用,诱导同系CD4+T细胞向Th2分化,发挥CCR7-CD45RO+效应性记忆性T细胞的功能。
- A prefetching policy in memory control system is proposed, which uses the idea of stream buffer proposed by Jouppi. 结合目前龙芯2号处理器系统总线的相关特征,提出了一种在存储控制系统内部实现的写缓存技术以提高系统的有效访存带宽。
- The computer stops. There's an error, and the central memory has picked it up; it cancels everything. There are no innocents to be saved, in this story. Start again. 计算机停了。报错,中央内存收到信息,一切都取消了。这个故事里没有等待拯救的无辜者。重头再来。
- Using FPGA to Implement DDR Memory Controller Scien? 利用FPGA实现DDR存储器控制器
- The first model is based on the expression of CCR7 defined two subsets of memory cells: central memory OCM) and effector memory cells (TEw)- Champagne et al. TcM表达CCR7,缺乏迅速反应的效应功能,但能对细胞因子或病原进行快速的反应并成熟为TEM,失去CCR7的表达,获得组织归巢受体,并大量分泌细胞因子。
- Recent studies have shown that memory T cells could be divided into central memory T cells and effector memory T cells, which were different in distribution, function and biological characteristics. 近年来的研究表明,记忆性T细胞可以被进一步划分为中枢记忆性T细胞和外周记忆性T细胞2个亚群,它们的分布和功能迥异,在生物学特性上也不尽相同。
- The basic thought and design schem of the memory control system to the height of cutting drum of shearer is elaborated,which offers a refrence to the design of automatic control system of shearer. 论述了采煤机滚筒高度记忆控制的基本思想,提出了设计方案,对采煤机自动控制系统的设计具有一定参考意义。
- Major issues for implementation of the video, the audio packetizer, and the TS multiplexer are discussed, such as time matching, multiplexer scheduling, stream synthesis, and memory control. 本文讨论了视音频打包与复用的关键技术，包括时序匹配，复用时序与逻辑，码流合成以及缓存控制等。
- The memory controller offers dedicated locks to limit access to SMRAM memory only to system firmware (BIOS). 内存控制器提供独用的锁定机制，来限制只有系统固件(BIOS)能访问SMRAM。
- The technology is very useful in designing ASIC's and SOC's,where embedded memory controllers are needed. 这种设计方法可广泛应用于ASIC芯片、SOC系统等需要嵌入存储控制器的场合。
- The DMMU consists of address translation unit (ATU) and double data rate (DDR) memory controller. 分散式记忆体管理单元包含位址转换单元和双倍资料率记忆体控制器。
- cache memory control communication 高速缓冲存储器控制通信
- Such values are central to our way of life. 这些价值对于我们的生活方式是至关重要的。
- The target of DFI standard is a kind of between logic of definition memory controller and PHY interface general interface. DFI规范的方针是界说存储节制器逻辑和PHY接口之间的一种通用接口。
- A demo system with the name, uCRISC, is designed based on SRISC. The system consists of SRISC processor, Wishbone bus, memory controller, and otherperipherals. 设计了基于SRISC的演示系统uCRISC，该系统包括S班SC微处理器、Wishbone总线、内存控制器以及计时器、中断控制器等外设;
- She stay in a small hotel near Central park. 她住在中央公园附近的一家小旅馆。
- According to the timing characteristics of SDRAM, the design makes use of a VHDL state machine,with focus on the implementation of techniques of multi-port memory controller. 根据SDRAM器件的控制时序特点,采用VHDL状态机的设计方法实现了多端口存储控制器的技术。
- Choose a central location for your house. 把你的家选在一个便利的地方。
