It applies multiple clocks on different pipeline parts basing on their logic complexity, and provides a parallelism on the slow part for throughput compensation.

• 它允许流水线模块根据各自逻辑复杂度选择不同的工作频率；通过提高简单模块的工作频率，并增加复杂模块的并行度，以实现流水线的指令吞吐率的优化。