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- TVS diode Chip Scale Package 瞬态电压抑制二极管覆晶晶片微型封装
- Stress analysis on gold wire of chip scale package 芯片尺度封装中焊线的应力分析研究
- The manufacture of solder bump is one of the key technologies for area array packaging (AAP) such as ball grid array (BGA), chip scale packaging (CSP) and flip chip (FC). 钎料凸台的制造是球栅阵列封装(BGA, ball grid array)、芯片尺寸级封装(CSP, chip scale packaging)及倒装芯片封装(FC, flip chip)等面阵封装的关键技术之一。
- Dual In-line Memory Module with Wafer Level Chip Scale Package 在内的芯片组大厂注意而成为内存模块新标准。晶圆级封装的内存模块
- W.W. Lee, L.T. Nguyen, and G.S. Selvaduray, “Solder Joint Fatigue Models: Review and Applicability to Chip Scale Packages,” Microelectronics Reliability, Vol. 40, pp. 231-244, 2000. 刘宏毅，金属受随机负载作用下之疲劳分析模式与探讨，国立台湾大学机械工程研究所硕士论文，1998。
- wafer-level chip scale packaging 圆片级芯片尺寸封装
- The diode chip is coated with a thin layer of hard glass which eliminates the need for a hermetically sealed package. 二极管片涂上一薄层硬玻璃，所以无需再用密封的管壳。
- At normal operating voltage, the TVS diode is inactive, like an open circuit. 雪崩崩溃二极管是以反向电流的方式,连接在线路上。
- chip scale package (CSP) 芯片尺寸封装
- Chip scale package 芯片规模封装
- CSP(Chip scale package) 芯片级封装（CSP）
- Stacked chip scale package 叠层芯片尺寸封装
- The IGBT as well as the diode chip are based on SPT (soft punch through) technology. 这里的IGBT和二极管二者的芯片都是基于SPT（软穿通）技术。
- TVS diode limits voltage spike to 瞬态电压抑制二极管与离子气体放电管
- Chip scale packaging 芯片规模封装技术
- The WLP technology that initiates processing from Wafer-Level and finishes in chip scale will be applicable on a daily broadening scale in plane array FCP. 在圆片规模上开始加工,结束于芯片规模的圆片级封装技术将在面型阵列倒装芯片的封装中得到日益广泛的应用。
- 11. The diode chip is coated with a thin layer of hard glass which eliminates the need for a hermetically sealed package. 二极管片上涂上了薄薄一层硬玻璃，所以无需再用密封的管壳。
- New diode chip sorting machine and sorts the method researeh 新型二极管芯片分拣机及分拣方法研究
- He is a great guy, a chip off the old block. 他是一位好人，就像他父亲一样。
- She made a guest appearance on his TV show. 她在他的电视节目中出场客串。
