The device is implemented in a two-level polysilicon E/D NMOS technology with active area of 13.28mm2. The architecture of the chip allows variable time-slot applications.

• 器件采用双层多晶硅E/DNMOS工艺制作；芯片有效面积为13.；28mm~2。 芯片系统结构具有可变时隙功能。