The generated programmable core contains logic block arrays of 4 inputs LUT and routing resources containing connection boxes of full connectivity and switch boxed based on unversal structure.

• 所生成的可编程核包括由4输入LUT组成的逻辑单元阵列以及全连通的连接盒和基于Universal结构的开关盒,并且可以具有非均匀布线结构。