The objective of this research is the former-end hardware design for the 64-bit RISC(Reduced Instruction Set Cpomputer)CPU core and the implementation and verification of the design on FPGA(Field Programmable Gate Array).

• 本研究的目的是进行64位的精简指令集中央处理器的前端硬件设计，并将此设计在FGPA上实现以通过实际的电路验证。