The proposed architecture algorithm requires only 11% number of multipliers and 9% number of adders compared with the direct implementation approach in N=256 FFT/IFFT .

• 此结构算法处理N=256点FFT/IFFT时，与直接处理算法相比，仅需要DSP硬件调制处理的11%25乘法器和9%25的加法器。