This thesis presents a circuit architecture to realize clock recovery for fast Ethernet application, including system architecture, modified Mueller Muller algorithm for 100BASE-TX, phase detector for 100BASE-FX and multiple output charge pump PLL.

• 提出了一种快速以太网卡芯片时钟恢复电路的设计 ,包括体系结构、用于 10 0BASE tx的改进MuellerMuller算法、用于 10 0BASE FX的鉴相器以及产生多相时钟的电荷泵锁相环。