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This paper expounds the method that designs Bus Interface Unit(BIU) by the new techniques, the key unit in MIL-STD-1553B data bus system. 本论文论述了用新技术来设计MIL-STD-1553B总线系统中的关键部件总线接口单元的设计方法。
There are five parts in PowerPc603e? microprocessor: Integer Execution Unit, Floating Point Unit(FPU), Instruction(Data) Cache, Bus Interface Unit and Memory Manage Unit. PowerPc603e微处理器系统由定点执行单元、浮点单元、指令(数据)Cache、总线接口单元、存储管理单元组成，以流水和超标量方式执行指令。
The research work of this dissertation mainly includes:1. Based on the deep research of the PowerPC750 architecture and PowerPC 60X bus protocol, the dissertation presents the design of bus interface unit of the microprocessor. 1) 深入研究PowerPC750微处理器体系结构和PowerPC 60X总线协议,完成了“龙腾R2”微处理器总线接口部件的设计。
There are five parts in VEGA microprocessor, which hires five-stage pipeline: Integer Execution Unit (IEU), Memory Subsystem Unit (MSU), Registers, Pipeline Control Unit (PCU) and Bus Interface Unit (BIU). VEGA处理器由定点执行单元、储存子系统(MMU、I-Cache和D-Cache)、寄存器堆、流水线控制单元和总线接口单元BIU五部分组成,采用五级流水线执行指令。
PI-Bus and Its Bus Interface Unit Chip PI总线及其接口芯片
Parallel Interface Bus Interface Unit 并行接口总线接口装置
MTMIU Module Test and Maintenance Bus Interface Unit 模块测试和维护总线接口单元
bus interface unit 总线接口部件
Functionality in this area includes bus interface circuitry and a level2 cache. 本区域的功能包括总线接口线路和二级缓存。
LXT384is a octal T1/E1/J1line interface unit,which is applied in SONET/SDH. LXT384是一个用于SONET/SDH设备的八进制T1/E1/J1线路接口单元芯片。
Our TM BUS design is based on two sets of standards: IEEE STD 1149.1 and IEEE STD 1149.5. In section 2.1, we discuss in detail the architecture of our TM BUS. Fig. 2 shows its TIU (test interface unit or test controller). 简要介绍了测试维护总线TM- BUS(test and maintenance bus)及其应用 ,论述设计的 TM- BUS控制器的结构、实现及 TM-BUS控制管理机制。
This paper introduce the I2C bus interface of S3C44B0X, and connective method with EEPROM. 文章介绍了S3C44B0X的I2C总线接口,与EEPROM的连接方法。
In order to reuse easily ,this IP core uses the Avalon bus interface and completes the function simulation in Modelsim. 为了满足复用,该IP核采用Avalon总线接口,同时利用Modelsim进行了功能仿真。
Functionality in this area includes bus interface circuitry and a level 2 cache. 本区域的功能包括总线接口线路和二级缓存。
Details of the USB bus interface for program development of the principles, processes and routines. 详细介绍了对USB总线接口进行程序开发的原理、过程和例程。
The adpter is composed of a bus interface module,a logic control module,an encoder/decoder and a transceiver module. 红外无线串行通信适配卡有四个模块：总线接口模块，逻辑控制模块，调制解调模块，发射接收模块。
Due to no SPI serial bus interface in MCS51 scm, MCS51 scm couldn't use SPI bus interface apparatuses. 摘要MCS51系列单片机由于不带SPI串行总线接口而限制了其在SPI总线接口器件的使用。
MPC860 consists of three major blocks:the Embedded PowerPC core,the System Interface Unit(or SIU),and the Communications Processor Module(or CPM). MPC860包括三个主要部分：嵌入式PowerPC内核、系统接口单元、通信处理器模块。
Abstract: The logic analysis and circuit design of VME bus interface logic is introduced in the paper. 摘要：本文介绍了VME总线接口逻辑芯片的逻辑分析和电路设计。
Finally, according to the ATO's characteristic, the malfunction data display interface unit is designed which has HDLC communication controller. 最后,根据ATO的特点,设计出了带HDLC通信控制器的故障数据显示接口单元。