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- We described hardware architecture, flowchart and software design of the system. 详细描述了该系统的硬件结构、工作流程以及软件设计。
- Its hardware architecture is a multiprocessor, consisting of one microcomputer and four TRANSPUTERs. 其硬件结构是由一台微机和四台TRANSPUTER组成的多机系统。
- We propose an efficient hardware architecture for deblocking filter in H.264/AVC. 在这篇论文中，我们提出了一个有效率的H.;264先进视讯影像压缩去区块滤波器。
- Chapter 3 is an introduction to the hardware architecture of DSP TMS320C6211, software programming environment CCS and the DSP/BIOS. 第三章介绍了TI公司的DSP TMS320C6211的硬件结构、软件开发工具CCS以及TI公司推出的相对简单的实时操作系统DSP/BIO5。
- High reliable PXI Bus system is used to construct its hardware architecture and LabWindows/CVI is used as software development tool. 在此基础上,设计了一套基于虚拟仪器技术的多普勒导航雷达自动检测系统,硬件平台基于高可靠的PXI总线,软件采用Labwindows/CVI开发；
- The hardware architecture of general Automatic Test System (ATS) was studied and the importance of switch system in ATS was pointed out. 对通用自动测试系统ATS的硬件架构进行了研究,指出了其开关系统的重要性;
- In the transform field, based on the understanding of the integer DCT/IDCT and Q/IQ, this thesis proposed the relative hardware architecture. 在变换域，本论文分析了整数离散余弦正变换/反变换和量化/反量化的算法原理，并提出基于双变换复用的硬件架构。
- In this thesis, we focus on the RTCP packet and propose the hardware architecture of RTCP packet processor and generator. 本篇论文我们著重在RTCP封包部分，并且提出RTCP封包产生器与处理器的硬体架构，藉由硬体的加速，多人的视讯会议系统也能即时的处理。
- What’s more，the method can be implemented by a much fewer complexity hardware architecture，for it avoids LLR calculation in the traditional method. 在算法的实现中摒弃了传统信号检测LLR算法中的对数运算，易于低功耗低成本的硬件实现。
- Hardware architecture in compression and decompression can also share a 112-byte CAM memory, a 1048-byte SRAM and a 29-byte ROM. 将压缩与解压缩硬体架构资源共用后，共使用112位元组的CAM、1048位元组的SRAM与29位元组的ROM。
- According to the result of simulations and testings, the hardware architecture utilizing pipelining and interleaving parallel technologies is designed. 根据仿真结论和硬件实测数据设计了应用流水线和数据交织处理并行技术的硬件实现体系结构。
- An optimized hardware architecture of run lenth decoding,inverse scan,inverse quantization and inverse transform in AVS video decoder is presented. 提出了一种适用于AVS的游程解码、反扫描、反量化和反变换硬件结构优化设计方案。
- The performance of low-level hardware concurrency primitives, like compare-and-swap, differ fairly substantially from one hardware architecture to another. 至于低级硬件并发原语的性能,不同的硬件体系结构之间更是千差万别。
- After completing the whole hardware architecture, the circuit driver is developed to record and save seafloor environmental parameters in real-time mode. 在硬件架构搭建完成后，开发出相配套的电路驱动软件，实现对海底环境参数的实时记录与存储。
- The method of AD7542and single chip microcomputer system to realize procedure controled to current source is discribed,and hardware architecture and softwave design are provided. 介绍了利用12位分辨率数模转换芯片AD7542结合单片机系统实现程控电流源的设计方案 ,同时给出了显示电流值的实现方法
- The design of an SFN Adapter based on DVB-T with FPGA is presented in this paper.The hardware architecture and implementation scheme of the SFN Adapter is introduced. 摘要设计了一种基于FPGA实现的DVB-T单频网适配器，介绍了系统的硬件结构组成和实现方法。
- This paper describes the hardware architecture and software of the system. The software system consist of microcode for Fastbus system and upper layer control software. 本文描述了该系统的硬件结构和软件系统，软件包括快总线系统的微码软件和上层控制软件。
- At the same time, the traditional MTMS, including not only hardware architecture but also software system, cannot meet demand of every aspect, and display many disadvantages. 同时传统的移动目标监控系统，无论是硬件体系架构还是软件系统都已经不能满足各方面的需求了，暴露出很多的弊病，这些问题影响到系统的效率、可扩展性和维护性等。
- Technical property of the hardware architecture is better than Mark III and close to Mark IV, both of which are produced by TRW company.This system can recognize objects fr... 图像目标识别算法由知识型图像分割、基于子波变换的旋转不变性参数提取和神经网络分类器三部分组成；
- Therefore, in order to obtain the maximum performance, it is necessary to use all SPEs and to adapt the code to match the underlying hardware architecture. 但是，为了获得最优的性能，有必要使用所有的SPE，修改代码并使之与下面的硬件结构相匹配。
