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- instruction execution unit 指令执行部件
- The CPU execution unit has detected an invalid opcode (the part of the machine instruction that determines the operation performed). CPU执行单元检查到一个无效的操作码(决定执行操作的指令的一部分)。
- There are five parts in PowerPc603e? microprocessor: Integer Execution Unit, Floating Point Unit(FPU), Instruction(Data) Cache, Bus Interface Unit and Memory Manage Unit. PowerPc603e微处理器系统由定点执行单元、浮点单元、指令(数据)Cache、总线接口单元、存储管理单元组成,以流水和超标量方式执行指令。
- SIMD SIMD integer execution unit for MMX? Technology instructions. MMX技术指令的SIMD整型数执行单元。
- In other words, software interrupts always occur at the beginning of an instruction execution cycle. 换句话说,软体中断常常在指令运行周期的开始发生。
- Problems in the application of pipeline structures for CISC, such as irregular instruction set and long cycle of instruction execution, are discussed. 重点讨论了流水线技术在80C51这类CISC中的一些应用问题(如指令格式不规范、执行周期长等)及其解决办法。
- In the instruction execution pipeline stage, scalable pipeline technology was adopted to realize the video processing instruction. 为有效实现扩展指令,处理器执行级采用了可扩展流水级技术。
- Many embedded applications have little or no need for floating-point arithmetic, and software emulation of PowerPC floating-point instruction execution is usually more than adequate when it is needed. 很多嵌入式应用程序很少或者根本不需要浮点算法,而当需要的时候,对PowerPC浮点指令执行进行软件仿真就足够了。
- All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. 所有的寄存器都直接与算逻单元(ALU)相连接,使得一条指令可以在一个时钟周期内同时访问两个独立的寄存器。
- Force needed to add to the executer unit to actuate switch contact . 使开关触点回复到正常位置,所必需减少施加于操动器上的力。
- The study of ECU is emphasis, to understand its basic structure, to analyze sensor input signal treatment circuit and execution unit drive circuit, to analyze microprocessor. So, basic design tactics of hardware system is get. 重点是电控单元的分析,了解电控单元的基本结构,对传感器输入调理电路和执行器驱动电路进行分析,对微控制器的型号进行分析,从而获得电控单元硬件的基本设计技巧。
- There are five parts in VEGA microprocessor, which hires five-stage pipeline: Integer Execution Unit (IEU), Memory Subsystem Unit (MSU), Registers, Pipeline Control Unit (PCU) and Bus Interface Unit (BIU). VEGA处理器由定点执行单元、储存子系统(MMU、I-Cache和D-Cache)、寄存器堆、流水线控制单元和总线接口单元BIU五部分组成,采用五级流水线执行指令。
- When the IN instruction executes, the IBF bit is cleared and the data in the port are moved into AL. 当IN指令执行时,IBF位被清除,并且端口内的数据被送入AL。
- The LOCK instruction prefix locks out all other CPUs while the microcode for the current instruction executes, thereby guaranteeing data integrity. 在当前指令的微代码执行的时候,LOCK指令前缀把所有其他CPU关在外面,因此保证数据完整。
- privileged instruction execution [计] 特许指令执行
- Average Instruction Execution Time 平均指令执行时间
- The position of executer unit in case of executer unit reaching the limitation position. 当操动器到达极限时操动器的位置。
- Core can speculatively move the blue load instructions before the red stores, and can make full use multiple execution units. Core可以投机的将所有兰色的读操作提前到所有写操作之前执行,从而并行利用多个执行单元。
- Force needed to add to the executer unit to make the switch conact back to normal position. 使开关触点回复到正常位置,所必需减少施加于操动器上的力。
- A firmware downloadable high-speed architecture of RISC CPU IP core has been designed. The instruction executing speed of this RISC CPU is 4 times fast than classical PIC MCU. 研究并设计成功一种先进的可下载固件(Firmware)架构的高速RISC CPU IP核,本CPU核是传统的PIC微控制器处理速度的4倍,并且可以实现Firmware的升级和更新。