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- logical block diagram 逻辑框图
- logic block diagram 逻辑框图
- A DAU hardware block diagram is shown in Fig.3. 数据采集器DAU硬件的方框图如图3所示。
- This simplified block diagram is valuable. 这个简化了的框图很有用。
- DAU hardware block diagram is shown in Fig.3. 数据采集器DAU硬件的方框图如图3所示。
- The block diagram of a battery charger is shown in Fig. 1. 图一所显示的是电池充电器的方块图。
- In some ways, the block diagram resembles a flowchart. 在某些方面,块状的图表类似于一个流程图。
- Figure 1-26 is a block diagram of a typical digital electrometer. 图1-26为典型数字式静电计的方框图。其模拟部分与前面讨论的电路类似。
- For example, use a BEGIN.END pair of statements when including more than one Transact-SQL statement in a logical block. 例如;当在一个逻辑块中包含多个Transact-SQL语句时;请使用BEGIN.;END语句对。
- The Adaptec 48-bit logical block addressing (LBA) support enables use of disk drives exceeding 137 GB in capacity. Adaptec 48位逻辑区块寻址(LBA)能力可支持容量超过137 GB的硬盘。
- On the File menu, point to New, point to General, and then click Block Diagram. 在“文件”菜单上,依次指向“新建”、“常规”,然后单击“框图”。
- Instead of addressing sectors by their CHS (cylinder, head, sector) address they use LBA (Logical Block Addressing) mode. 他们使用LBA(逻辑块地址)模式,而不是通过CHS地址来定位一个扇区。
- This paper presents a new FPGA logic block, FDP, which is suitable for datapath circuits. 提出一种适于实现数据通路的FPGA逻辑模块。
- The receiver's block diagram, flowchart and performance simulation results are given in the paper. 给出了接收机结构框图、工作原理和性能仿真结果。
- Recently, you created a block diagram that makes the process easier to understand. 最近,您创建了一个能使该过程更易于理解的框图。
- The Basic Diagram, Block Diagram, and Block Diagram with Perspective templates are in the General category. 基本框图、框图和具有透视效果的框图模板位于“常规”类别中。
- The block diagram may be broken at convenient places to show important changes or complexities in the structure. 立体图可以在适当的地方剖开,以表示构造上重要的变化和复杂性。
- Please give the system design scheme of your design or both hardware design block diagram and software flow chart. 请给出你的设计框图,或同时给出硬件设计框图和软件流程图。
- Useful for a quick, high-level view of the parts of your project, a WBS is often shown as a block diagram. WBS通常显示为块关系图,这样就有助于从高层次迅速总览项目的各个部分。
- Figure 4 is a functional block diagram of a 2-axis MEMS integrated accelerometer. 图4所示为两轴MEMS整合的加速度计的原理框图。