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- This multiplier used modified Booth Algorithm, Wallace tree and 4- 2 compressor. 乘法器采用改进的Booth算法,简化了部分积符号扩展,使用Wallace树结构和4-2压缩器对部分积归约。
- Taking advantages of the merits of redundant Booth encoding and modified Booth encoding,the novel Radix?16 Booth algorithm of the structure can simply and quickly generate complicated multiples. 该结构所采用的新型Radix-16 Booth算法吸取了冗余Booth编码与改进Booth编码的优点;能简单、快速地产生复杂倍数.
- In this design, the use of modified Booth algorithm, circuit to deal with signed/unsigned operands, sign extension and special module to add partial products result in a faster multiplier , with a delay equivalent to 6 NOT-OR gate. 由于乘法器的设计中采用了修正的布斯 (booth)算法、符号数 无符号数处理机制、符号扩展处理电路以及特殊的部分积累加模块 ,所以乘法器的速度得到很大的提高 ,仅仅相当于 6个或非门的延迟
- modified Booth algorithm 改进Booth算法
- A high-speed 16bits*16bits multiplier has been developed, which introduces Modified Booth Arithmetic (MBA), Wallace Tree and 4:2 Compressor, Pseudo 4:2 Compressor and Square Root Carry-Select Adder. 根据承担的科研项目的需要实现了高速16bits×16bits的乘法器，采用华东师范大学硕士论文高速可配置基2 FFT处理器的FPGA实现研究了修正布斯编码、华莱士压缩树，4:2压缩器和伪4:2压缩器，平方根求和等新型结构。
- This paper provides the design method of a high speed fixed point multiplier. It employs Modified Booth Arithmetic(MBA), Wallace-Tree, 4:2 Compressor, pseudo 4:2 compressor and the Suqare Root Carry-Select Adder. 文章系统地研究了符号定点高速乘法器的实现算法和结构,采用了修正布斯算法,华莱士压缩树,4:2压缩器,伪4:2压缩器以及平方根求和结构。
- The paper presents a multiplier circuit based on Booth algorithm when the radix equals four by studying the Booth algorithm. The carry-save-array adder and the pipeline technique are drawn into the design for improving the circuit speed. 通过对 Booth 算法的研究,本文提出了一种基 4 Booth 算法的硬件乘法器电路,为了提高硬件乘法器电路的运算速度,将保留进位加法电路和流水线技术引入了该乘法器电路。
- The field programmable gate array(FPGA) simulation shows that compared to the multiplier with Radix?8 Booth algorithm,the speed of this multiplier is increased by 11% and its hardware resource is reduced by 3%. 经现场可编程逻辑器件仿真验证表明;与采用Radix-8 Booth算法的乘法器相比;该乘法器速度提高了11%25;硬件资源减少了3%25.
- A 32-bit multiplier is presented in which many methods, such as Booth algorithm, 4-2 compressors, Wallace tree algorithm,and carry-lookahead adder, are applied, which results in high speed performance. 该文提出的32位乘法器,采用了Booth编码、4-2压缩器、Wallace树算法以及超前进位加法器等多种算法和技术,在节约面积的同时,获得了高速度的性能。
- Booth algorithm of binary multiplication 二进制乘法的布斯算法
- partially redundant booth algorithm 局部冗余贝斯算法
- He banged into a telephone booth and hurt his leg. 他撞在了一个电话亭上，伤了腿。
- The car dashed against a telephone booth. 那车子猛地撞在一间电话亭上。
- There is a telephone booth near the cinema. 电影院附近有一个电话亭。
- He went into the phone booth and dialed the number. 他走进电话亭拨了号码。
- The car has been modified for racing. 这辆汽车已改装为赛车。
- I'll give him a call from the phone booth on the corner. 我到街角的电话亭给他打个电话。
- Would you please watch over my booth? 请您照料一下我的摊位好吗?
- The machine has been extensively modified. 这机器已被大规模地改造过。
- The multiplier unit adopts the BOOTH algorithm and carry lookahead adder; 在乘法器单元中采用BOOTH算法和先进进位加法器相结合的单元设计；
