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- In this paper ,the SoC on chip bus is analyzed bycomparison of AMBA, AVALON, OCP and WISHBONE . 本文通过对AMBA, AVALON, OCP,WISHBONE等SoC总线的比较,分析了SoC片上总线技术。
- And OCB (On Chip Bus) is most often used technique for SoC communication and IP cores connection. 片上总线(On Chip Bus)是SoC系统连接IP核,有效实现系统部件之间通信的主要手段。
- SoC (System on Chip) is satisfied with the demand. 片上系统SoC(System onChip),就是在这种环境下应运而生的。
- Hardware structure: The encryption card is made up of CPU, USB bus interface, flash store chip, WNG4 randomizer and IC card reader. 加密卡硬件结构: 该加密卡主要由主CPU、计算机USB总线接口、FLASH存储芯片、WNG4随机源和IC卡读卡器等组成。
- Cipher Card is a hardware module based on bus interface of computer and offering cryptogram service function. 加密卡是基于计算机总线接口的、提供密码服务功能的硬件模块。
- The method of intercommunication among single chip computers was discussed. The system is composed of single chip computer module, share-memories, share-I/O,bus interface and arbitrator. 讨论了80C196MC单片机系统多微机互联方案,该系统以单片机为主模块,共享存储器、共享I/O、总线接口及仲裁器构成。
- Functionality in this area includes bus interface circuitry and a level2 cache. 本区域的功能包括总线接口线路和二级缓存。
- It's the best time to stock up on chips. 正是个疯狂抢购土豆片的大好时机。
- PI-Bus and Its Bus Interface Unit Chip PI总线及其接口芯片
- The Measurement of Average Power for Non-Sinusoidal Waveforms Based on Chip Microcomputer. 基于单片机的非正弦波平均功率的测量。
- ACET devices can be readily integrated on chip into a microsystem.This offers insight into designing ACET lab-chips. 研究结果为设计交流电热效应芯片实验室提供了参考依据。
- The development condition of 55 dtex bright trilobal profiled FDY on chip spinning FDY production line is introduced. 介绍在切片纺FDY生产线上开发55dtex有光三叶异形全拉伸丝。
- This paper introduce the I2C bus interface of S3C44B0X, and connective method with EEPROM. 文章介绍了S3C44B0X的I2C总线接口,与EEPROM的连接方法。
- The influences of some cutting parameters on chip curvature and mechanism of chip-curling are also studied. 本文还研究了一些切削参数对切屑卷曲影响规律及切屑卷曲过程的机理。
- In order to reuse easily ,this IP core uses the Avalon bus interface and completes the function simulation in Modelsim. 为了满足复用,该IP核采用Avalon总线接口,同时利用Modelsim进行了功能仿真。
- Hardware and software co design technique is the critical technique in system on chip design. 硬件 /软件协同设计技术 (HW/SW Co-Design)是实现“片上系统”(So C)设计的重要环节。
- Functionality in this area includes bus interface circuitry and a level 2 cache. 本区域的功能包括总线接口线路和二级缓存。
- A high performance SDRAM controller orienting to system on chip is designed by analyzing the access of SDRAM. 摘要在分析了SDRAM存取原理之后,提出并设计了一种面向片上系统的高性能SDRAM控制器。
- Details of the USB bus interface for program development of the principles, processes and routines. 详细介绍了对USB总线接口进行程序开发的原理、过程和例程。
- Shashi Kumar,Axel Jantsch,et al.A Network on Chip Architecture and Design Methodology. IEEE 2002. 陈国良,吴俊敏,章锋,章隆兵编著.;并行计算机体系结构