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- sequential circuit testing 时序电路测试
- BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with flip-flop as core. 面向逻辑级描述的同步时序电路 ;以触发器为核的电路划分算法BWFSF将电路划分为大功能块 .
- In this thesis, we use the oscillation ring test methodology to test stuck-at faults for sequential circuits. 摘要:在此篇论文中，我们利用振荡环测试的原理来侦测序向电路上之定值障碍。
- BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with fli. 面向逻辑级描述的同步时序电路,以触发器为核的电路划分算法BWFSF将电路划分为大功能块。
- Combination of circuit testing algorithm D thesis 2, easy to learn U.S. D algorithm relevant content! 组合电路测试中的D算法论文2，便于大家习D算法相关的内容!
- The hardware circuit test indicates that the designs satisfying the system request. 硬件电路测试表明所设计的硬件系统满足要求。
- In general, the sequential circuits by combinational circuits and storage circuit two parts. 从总体上看，时序电路由组合电路和存储电路两部分组成。
- A unit that can be placed in a multiconductor circuit (say, between a computer and a modem) to provide terminal connections for circuit testing. 放置在多线电路中的一种装置(如计算机和调制解调器间),为电路测试提供终端连接。
- Sometimes inverse current impulse can be observed during the short circuit test of large power generators. 大容量整流型发电机短路试验中有时能观察到电流反冲现象。
- This paper is a discussion on some teaching methods of the simplification for Karnaugh map,the analysis of sequential circuit and the teaching of integrated circuits. 对数字电路中卡诺图化简、时序电路分析和集成电路教学等三个问题的教学方法进行一定的分析和探讨。
- This paper introduces a coil short circuit test set which is made of inductionoscillator generator,coupling circuit and annunciator circuit. 介绍一种由感知振荡器电路、耦合电路和报警电路组成的线圈匝间短路测试仪。
- Type 37TF includes an internal resistor wired in parallel with the contacts which serves as an aid to factory circuit testing where the contacts are open at room temperature. 型号37TF包括有一个内部电阻，这个电阻与（一对）触点并联连接，这对触点对出厂前的电路检测能提供帮助，在室温下，这对触点是断开的。
- With the design procedure of sequential circuits, varieties of Schmitt circuits based on integrated gate circuits are systemati-cally investigated, and some new designs are found. 利用时序电路的设计方法,本文系统地研究了基于集成门电路的各种施密特电路,并发现了一些新的设计方案。
- The partial scan design methodology has been recognized as a cost-efficient technique to improve the testability of sequential circuits. 部分扫描设计之理论业已受大家之公认,能够经济而有效率的改进序向电路之可测试性。
- Abstrcat>This paper analyses five rules of state assignment for designing sequential circuits comprehensively and assignment techniques for interlink states chains. 本文全面分析了时序逻辑电路设计中的5个状态分配规则和相邻状态链分配技术。
- The time used to test the machine or system to insure that no faults exist or malfunctions are present by using special diagnostic routines for circuit testing or to discern status of conditions or components. 用于测试机器或系统，保证其无故障运行或无工作不正常所需的时间，其间采用特殊诊断例行程序来检测电路，判定条件状态或部件状态。
- The in circuit test is a kind of automatic test technique for PCB.Taking Italian testing equipment S20ATE as an example,this paper describes the basic principles of this technique, and introduces its system architecture and test programming method. 电路在线测试技术是一种电路板的计算机自动测试技术。 本文以意大利的自动测试设备S20 （S20ATE）为例， 阐述了这种技术的基本原理， 同时介绍了S20ATE的系统结构和编程使用办法。
- Discussions about sequential circuit design 一个时序电路设计实例分析
- Among the verification tasks of sequential circuits, FSM initialization is one of the most important problems.It ensures that a sequential circuit starts from a correct initial state. 摘要:循序电路的验证工作中，初始化是其中的一个重要议题，它确保电路能从正确的初始状态开始运作。
- synchronizing sequential circuit 同步时序电路
