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- single clock signal 单时钟信号
- The device always generates the clock signal. 时钟信号总是由设备端生成的。
- The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal. 你的微型计算机执行程序的速度将与你的时钟信号的速度成线性关系。
- The transition from voltage to no voltage is referred to as the trailing edge of a clock signal. 电感从一定值下降到0值的跃迁叫做时钟信号的后沿。
- Another unique architectural feature is the memory system which allows an instruction fetch and at the same time a data access by each individual core at every single clock cycle. 另一个独特的构架特性是内存系统,它允许一个取指,并在同一时间,每一个核可以读取数据在每一个单独的时钟周期内。
- The system can hold the 'clock' signal inactive to inhibit the next transmission. 系统拉低时钟线,将禁止下一次传输。
- These objective functions were considered efficient before since the latencies of interconnects were within single clock cycle or even could be neglected. 由于过去晶片内部连线的延迟所需要的时间是可以忽略的，这样的方程式被认为是足够的。
- The key difference between these two is that the DCE device provides the clock signal for the communications on the bus. 这两种类型之间的主要差异是DCE装置在汇流排上提供通讯使用的时脉信号。
- Its function is to provide a latching switch action upon sensing an input threshold voltage, with reset accom-plished by an external clock signal. 它的功能是当感应到输入电压界限时提供一个锁存开关，通过外部时钟信号完成复位。
- The clock signal with precise duty cycle produced by DCM is used in the bus data DDR transmission.The simulation results are also given. 利用DCM产生的具有精确占空比的时钟信号,给出了其在DDR总线数据传输中的应用,并给出了仿真结果。
- Thus, the clock signal passing between the FPGA and the ADC's for each channel will physically clock in this frequency range. 这样，FPGA和AD转换器之间的时钟频率物理上落于这个频率窗口之内。
- For synchronous connections, where a clock signal is needed, either an external device or one of the DTEs must generate the clock signal. 为了达到同步的连线，需要有时钟讯号才行，有可能是一台外部设备或者其中一台资料终端设备必须产生时钟讯号。
- A method of realizing clock signal by CPLD during GPS desynchronization.Automation of Electric Power Systems,2003,27(17):64-67. GPS失步后时钟信号的CPLD实现方法.;电力系统自动化;2003;27(17):64-67
- Intensity and pulsewidth of incident signal, the length of dispersion shift fiber (DSF) and walk off between incident and clock signal influenced the output clock intensively. 重点分析了色散位移光纤的长度和入射信号的脉宽和强度、以及走离对输出时钟信号的影响;
- The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. 转换过程和数据采集过程通过CS和串行时钟信号进行控制,从而为器件与微处理器或DSP轻松接口创造了条件。
- Time clock signal source directly fetches from clock signal of PCI bus in the computer system or signal generator, which can generates high frequency time clock signal. 该时钟信号源直接取自于该电脑系统中PCI总线的时钟信号或是一可产生高频时钟信号的时钟信号产生器，用以供应该计数电路所需的输入时钟信号。
- Serial transmission over long distance requires that the timing information for the receiver be transmitted together with the data so that a separate clock signal is not required. 由于接受者需要定时信息，长距离的串行传输为了避免单独传时钟信号需要把定时信息和数据一起传输。
- Some basic circuits with single and dual rail structure used to realize all clocked signals are designed,whose cascode types are also presented. 设计了实现全部钟控信号的基本单元电路;这些电路包括单轨和双轨结构;并给出了它们的多种级联方式.
- The control signals for the ac-excitation must be non-overlapping clock signals. 控制信号为交流励磁时必须不能重复时钟信号。
- The letter was written on a single sheet of paper. 这封信只用一张纸写成。
