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- BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with flip-flop as core. 面向逻辑级描述的同步时序电路 ;以触发器为核的电路划分算法BWFSF将电路划分为大功能块 .
- BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with fli. 面向逻辑级描述的同步时序电路,以触发器为核的电路划分算法BWFSF将电路划分为大功能块。
- LIU Ying,FANG Zhen-xian,FANG Peng-jun.Adiabatic ratioless dynamic flip-flops and synthesis for synchronous sequential circuits[J].J of Electronic and Information Technology,2002,24(12):1967-1972. [9]刘莹.;方振贤
- A CORRECTIONAL METHOD OF NON-SELF-STARTING SYNCHRONOUS SEQUENTIAL CIRCUIT 无自启动能力同步时序逻辑电路的校正
- Parallel Test Pattern Based Fault Simulation Method for Synchronous Sequential Circuit 基于测试码并行的同步时序电路故障模拟方法
- synchronizing sequential circuit 同步时序电路
- Research and Implementation of the Fault Simulation Speed-up Method for the Synchronous Sequential Circuit 同步时序电路故障模拟加速方法研究与实现
- Novel Circuit-parallel Test Generation Algorithm for Synchronous Sequential Circuit 面向同步时序电路的电路并行测试生成算法
- Multiple Fault Testing of Synchronous Sequential Circuit with Dynamic Boolean Equation Method 同步时序线路多故障测试的动态布尔方程方法
- synchronous sequential circuit 同步顺序电路
- A FANOUT-SOURCE BASED FAULT PARALLELISM FAULT SIMULATOR FOR SYNCHRONOUS SEQUENTIAL CIRCUITS 基于扇出源的同步时序电路故障并行故障模拟器
- ADIABATIC RATIOLESS DYNAMIC FLIP-FLOPS AND SYNTHESIS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS 绝热无比型动态触发器和同步时序电路综合
- Design of Synchronous Sequential Circuits Based on the K-map of Next State Functions of Flip-flops 基于触发器次态函数K图的同步时序电路设计
- Stability Condition of Adiabatic Memorial Unit and Adiabatic Synchronous Sequential Circuits in Three-phase-clock 绝热电路稳定性和三时钟绝热同步时序电路
- A Combination of Partial Reset and Observation Point Insertion for Synchronous Sequential Circuits 采用独立复位信号的同步时序电路可测试性设计
- A new method of designing synchronous sequential logic circuits is propsed. 提出了一种设计同步时序逻辑电路的新方法。
- Applying these principles to synchronous sequential machines, the methods for designing TSC Moor and Mealy type sequential machines are also derived, The parity code and single fault set are in the author s design. 本文将这些设计方法应用于同步时序机,进一步给出了设计全自检Moor型时序机和Mealy型时序机的方法。 上述设计采用的编码是奇偶码。
- In general, the sequential circuits by combinational circuits and storage circuit two parts. 从总体上看，时序电路由组合电路和存储电路两部分组成。
- Design Basis of Synchronous Sequential Logical Circuit 同步时序逻辑电路设计基础
- In this thesis, we use the oscillation ring test methodology to test stuck-at faults for sequential circuits. 摘要:在此篇论文中，我们利用振荡环测试的原理来侦测序向电路上之定值障碍。
