后端总线逻辑。访问内部统一二级处理器缓存的后端总线接口逻辑。

后端总线逻辑。访问内部统一二级处理器缓存的后端总线接口逻辑。的英文翻译

基本释义

• BBL Back-side Bus Logic. Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.