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- 乘法器采用改进的Booth算法,简化了部分积符号扩展,使用Wallace树结构和4-2压缩器对部分积归约。This multiplier used modified Booth Algorithm, Wallace tree and 4- 2 compressor.
- 模拟验证表明,与采用传统Wallace树结构和改进Booth二阶算法的乘法器相比,该乘法器的乘法延时减少了23%,功耗降低了17%,面积减少了20%.Compared to the conventional multiplier with modified Booth algorithm for radix-4 and Wallace tree architecture,the proposed techniques employed in the multiplier reduces 17%25 of the power dissipation and 23%25 of the multiplication time,and the area of multiplier is reduced by 20%25.
- 改进to improve
- 对于SA-DCT,采用Booth算法对DCT系数编码,用可编程处理器的概念实现不同长度DCT的变换,同时提出了一种新颖的转置寄存器阵列实现所必需的转置操作,整个结构面积为12500门,最大功耗为2.54mW。Second, for the design of SA-DCT, booth encoding is introduced for coefficients of DCT, and the design concept of programmable processor is adopted to computing various-length DCT while a novel transposed register array is proposed to implement the transpose operation necessary for SA-DCT. The proposed SA-DCT core costs about 12500 gates with the maximum power consumption of 2.54mW.
- 改进的modified
- 改进措施corrective measure
- Booth算法Booth algorithm
- 高基Booth算法high radix Booth algorithm
- Booth编码算法optimal Booth coder
- 改进Booth编码Modified Booth encoder
- 冗余Booth算法redundant Booth algorithm
- 改进的Booth编码improved Booth encoding
- 棋类博弈算法的改进Improvement on Algorithm of Chess Game
- 改进算法improved algorithm
- booth’S乘算法与基2{?,0,1}记数制系统BOOTH'S ALGORITHM AND RADIX TWO {(1|-),0,1} NUMERATION SYSTEM
- 改进型booth华莱士树的低功耗、高速并行乘法器的设计Low Power and High-Speed Parallel Multiplier Design Using Modified Booth Wallace Tree
- 算法改进algorithm improvement
- 策略改进算法policy improvement algorithm
- 改进BP算法improved BP algorithm
- 改进GS算法improved GS algorithm
