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Especially, the quality of gate dielectric layer determines the reliability and electrical performance of ultra large scale integrated (ULSI) circuit. 特别是闸极介电层的品质能决定ULSI电路的稳定度与电特性表现。
We focus on how the processes in repaid thermal processor (RTP) affect the electrical characteristics quality of gate dielectric layer. 我们将会集中以快速热制程如何影响介电层电特性。
Tunneling allows voltage to flow from the control gate to the floating gate through the dielectric layer of oxide which separates them. 允许从隧道流电压控制的浮动栅栅绝缘层氧化物通过分隔他们。
NTBI induced device degradation can be suppressed by a SiN capping layer between Poly-Si gate and high k dielectric layer. 在闸极与高介电常数介电层间使用氮化矽可有效抑制负偏压温度不稳定性的现象。
Results show that HfO 2 gate dielectric hold good electrical characteristics. 实验结果显示 :Hf O2 栅介质电容具有良好的 C-V特性 ,较低的漏电流和较高的击穿电压。
Ultra-thin Si 3N 4/SiO 2(N/O) stack gate dielectric with EOT of 2.1nm is fabricated successfully,and its characteristics are investigated. 成功制备了EOT(equivalentoxidethickness)为 2 1nm的Si3 N4/SiO2 (N/O)stack栅介质 ;并对其性质进行了研究 .
The reliability of strain silicon,gate dielectric and copper interconnection are discussed,and some new researches are presented. 简介了应变硅材料、栅介质的工艺及铜互连的可靠性,并对新的研究方向做了介绍。
For continued technology scaling, high k materials are required to replace SiO_2 as gate dielectric in the next generation metal oxide field effect transistors (MOSFET). 在过去二十多年里,Si基元器件的大小遵循Moore定律按比例的持续减小。对于下一代金属氧化物半导体场效应管(MOSFET)器件,原来的栅极介电材料SiO_2已经不再适合使用。
When an inhomogeneous plane wave is introduced into a dense dielectric layer, it can bounce between the two boundaries. 把一非均匀平面波引进折射率较高的介质层时，它会在上下界面间来回地“弹”射。
Dual damascene technology of Cu / low dielectric layer is introduced in this paper, andthis technology has been used in manufacturing DRAM and logic devices. 介绍了铜/低介电常数介电层的双嵌入式工艺,该工艺已大规模应用于动态记忆存储器(DRAM)和逻辑电路器件中。
By complementing the equivalent oxide thickness (EOT) of a 1.7nm nitride/oxynitride (N/O) stack gate dielectric (EOT=1.7nm) with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. 在国内首次将等效氧化层厚度为1·7nm的N/O叠层栅介质技术与W/Ti N金属栅电极技术结合起来;用于栅长为亚100nm的金属栅CMOS器件的制备.
And the conclusion is presented too.It is easy to design and manufacture waveguide filter using dielectric layer PBG structures. 利用介质层PBG结构来制作波导滤波器具有设计简单、易于实现的显著优点。
As reducing the gate length toward to submicron CMOS device, selecting a gate dielectric material to improve the electric characteristics and been demonstrated by using ISE-TCAD simulation tool. 从改变氧化层材料与线宽之方式对元件性能的提升并藉由ISE-TCAD 模拟工具来探讨。
Silicon oxide has been used as a gate dielectric of MOSFETs for more than forty years since MOSFET had been introduced due to its excellent stability, uniformity, and easy fabrication process. 自从金氧半导体场效电晶体被发明以来，二氧化矽巳经被用作为其闸极氧化层超过四十年之久，因为二氧化矽拥有极佳的稳定性和均匀度且制作过程较为简单。
We show the reflection and transmission behaviors when SPPs propagate along the metallic surface with one dimensional dielectric layer coated. 我们进一步讨论了表面等离子体激元在一维结构正入射时的反射性质，以及完全带隙的构造，和初步的实验结果。
While the top electrode is located on the third dielectric layer, in which each third dielectric layer and its top electrode compose a stack structure. 而上电极是位于第三介电层上，其中由每一第三介电层与其上的上电极组成一个堆栈结构。
Dual damascene technology of Cu/ low dielectric layer is introduced in this paper, andthis technology has been used in manufacturing DRAM and logic devices. 介绍了铜/介电常数介电层的双嵌入式工艺,该工艺已大规模应用于动态记忆存储器(RAM)逻辑电路器件中。
DPN process for MOS gate dielectric treatment 绝缘栅氮处理技术
nitride/oxynitride gate dielectric stack 氮氧叠层栅介质
As a vertically extended contact surface is formed between the said metallic pad and the dielectric layer in the dentritic structure, the contact surface and adhesion are increased. 由于在金属接线垫层及位于树枝状子结构中的介电层之间形成垂直延伸接触表面，因此扩大了接触面积而增强附着力；树枝状子结构在介电层的边缘部分不连续可有效截断而防止形成裂缝。