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- The parallel loading of the flip-flop can be synchronous (i.e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register. 触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟),这取决于移位寄存器的设计。
- The invention relates to a method and device for generating synchronous clock signals for writing operation in disk drive. 本发明涉及在磁盘驱动器中产生用于写操作的同步时钟信号的方法和装置。
- In binary synchronous communication, the use of clock pulses to control synchron ization of data and control characters. 在二进制位同步通信中,使用时钟脉冲来控制数据和控制字符的同步。
- Trigger control circuit from complex programmable logic device (CPLD), ICL7135CN, the clock pulse circuit and optocoupler inverter constituted. 触发控制电路由复杂可编程逻辑器件(CPLD),ICL7135CN,时钟脉冲电路、反相器和光耦构成。
- Design and Realization of Embedded Synchronization Clock System. 嵌入式同步时钟系统的设计与实现。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一个高->低时钟跳变时,(或者在最后一个时钟脉冲的下降沿之后)主机将时钟拉低,键盘/鼠标不必重新传输任何数据。
- DDR SDRAM is a high speed and largecapacity memory,but because of the need of synchronous clock and the characteristic that it is controlled by control command,there must be a controller between the system and DDR SDRAM. DDR SDRAM是一种大容量,高速度的同步动态存储器,但是由于其对同步性的要求以及需要由控制字来控制的特点使得他与系统之间必须有一个接口来实现时钟同步和对DDR SDRAM进行控制。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/ mouse does not need to retransmit any data. 如果在第一个高->时钟跳变时,(者在最后一个时钟脉冲的下降沿之后)机将时钟拉低,键盘/标不必重新传输任何数据。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the a last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一个高->低时钟跳变时,(或者在最后一个时钟脉冲的下降沿之后)主机将时钟拉低,键盘/鼠标不必重新传输任何数据。
- Note that a set of lights attached to O1, O2, O3 would display the numbers of full clock pulses which had been completed, in binary (modulo 8), from the first pulse. 注意,一组接在O1,O2,O3上的灯泡将以二进制(模8)形式显示第一个脉冲以来已完成的完整时钟脉冲数。
- A microprocessor designer may decide to make all instructions last five clock pulses. 微处理机设计人员可以决定使所有的指令持续五个时钟脉冲。
- Programmable output clock pulse width 输出脉冲宽度可编程
- suppressed clock pulse duration modulation 压缩时钟脉冲宽度调制
- Summary of the Underwater Ranging Using Synchronous Clock 同步钟式水下测距综述
- multiphase clock pulse generator 多相时钟脉冲发生器
- Research of Multimode Digital Synchronous Clock Technology 多模式数字同步时钟产生技术研究
- An unwanted false electronic pulse. 一种不希望有的假电子脉冲。
- To get the current temperature, you must write 35 fixed bytes into the port register.The sensor expects 16 clock pulses on the SCK line while the SS# is low. 为了取得当前温度;你必须写35个固定的字节到端口寄存器.;当ss低的时候,该传感器预计16个时钟脉冲在串行时钟线。
- An online delay?evaluation approach, namely average delay window(ADW) is introduced for networked control systems, which can characterize the time delays without any synchronized clock in the network and prior assumptions about time delays. 从网络控制系统的实际应用出发,在不附加网络同步时钟和对时延特征的离线假设下,运用通讯技术中的网络协议对网络时延进行在线估计;
- I didn't wake up until I heard the alarm clock. 直到听到闹钟的铃声我才醒来。