您要查找的是不是:
- A new method of designing synchronous sequential logic circuits is propsed. 提出了一种设计同步时序逻辑电路的新方法。
- synchronous sequential logic circuits 同步时序逻辑电路
- A New Method of Designing Synchronous Sequential Logic Circuits 一种设计同步时序逻辑电路的新方法
- A New Method to Design Synchronous Sequential Logic Circuit 同步时序逻辑电路设计的一种新方法
- A STUDY ON DESIGNING OF SYNCHRONOUS SEQUENTIAL LOGIC CIRCUITS 同步时序逻辑电路设计方法的研究
- Design Basis of Synchronous Sequential Logical Circuit 同步时序逻辑电路设计基础
- Flip-flops are a key componemt and memory cells of sequential logic circuit. 触发器是构成时序逻辑电路的存储单元和核心部件。
- Sequential logic synthesis is an important part of RTL synthesis system design. 时序逻辑综合是RTL综合系统设计中的一个重要部分。
- BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with flip-flop as core. 面向逻辑级描述的同步时序电路 ;以触发器为核的电路划分算法BWFSF将电路划分为大功能块 .
- BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with fli. 面向逻辑级描述的同步时序电路,以触发器为核的电路划分算法BWFSF将电路划分为大功能块。
- The second is where you have to integrate the loop closely with the sequential logic. 第二点是,人们必须将一些控制环与顺序逻辑控制更紧密地集成。
- Complex programmable logic device (CPLD), usually used to develop ASIC, is widely used in digital system to accomplish complex combinational and sequential logic. 复杂的可编程逻辑器件(CPLD)广泛地用于数字系统中,常用作设计自己的专用集成电路,可实现复杂的组合逻辑和时序逻辑。
- Applying these principles to synchronous sequential machines, the methods for designing TSC Moor and Mealy type sequential machines are also derived, The parity code and single fault set are in the author s design. 本文将这些设计方法应用于同步时序机,进一步给出了设计全自检Moor型时序机和Mealy型时序机的方法。 上述设计采用的编码是奇偶码。
- LIU Ying,FANG Zhen-xian,FANG Peng-jun.Adiabatic ratioless dynamic flip-flops and synthesis for synchronous sequential circuits[J].J of Electronic and Information Technology,2002,24(12):1967-1972. [9]刘莹.;方振贤
- By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis. 提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ;重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 .;此方法有效地利用了已有的成熟技术;为缩短 RTL综合的开发时间提供了一种有效途径
- The Deka value T gate is a kind of multi functional and general logical unit. It has independent perfection function,and it can realize any combination logic and sequential logic. 十值T门是一种多功能通用逻辑部件;具有独立的功能完备性;它可以实现任何组合逻辑和时序逻辑.
- Computer aided logical design(CALD) software design rapidly and exactly combinational logical and sequential logical circuits. 该软件可以快速、准确、可靠地设计出多输入多输出液控逻辑回路,设计结果可以达到最优。
- The Race and Hazard in the Sequential Logic Circuit 时序逻辑电路中的竞争冒险
- At this point your logic is at fault. 在这一点上你的推理是错误的。
- A Rapid Design Approach of Sequential Logic Net 一种时序逻辑网络的快速设计方法