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CDL is a wide-spreading computer hardware description language. CDL语言是国际上广泛使用的计算机硬件描述语言,CDL/MP是CDL语言的扩充。
IC VHDL: Very high speed integrated circuit Hardware Description Language. 超高速集成电路硬件描述语言。
An 8 bits SCM was designed with VHSIC hardware description language (VHDL). 课题采用硬件描述语言VHDL设计了8位单片机系统。
The controller is designed with hardware description language VHDL at RTL level, and implemented with single CPLD. 控制器采用VHDL(超高速集成电路硬件描述语言)语言在RTL(寄存器传输级)级设计;并在单片CPLD(复杂可编程逻辑器件)上实现.
A method of VHDL,a high level behavioral hardware description language,is applied in design. 设计过程是用VHDL语言来描述硬件功能，对行为特性的高层次的描述简化了设计过程。
The Viterbi algorithm and deskew algorithm are implemented using Verilog hardware description language. 本论文硬件实现了适用于1000BASE-T收发器的Viterbi译码器和数据对齐模块。
The paperfirstly introduces the advantage of CPLD(complex programmable Logic Device) andVHDL(VHSIC Hardware Description Language). 本文首先对 CPLD(复杂可编程逻辑器件)和 VHDL 进行了简要的介绍,并分析了使用 CPLD 进行电子设计的优点。
Direct Digital Frequency Synthesis(DDS) technology is realized on complex programmable logical component(CPLD) with hardware description language. 在复杂可编程逻辑器件(CPLD)上,用硬件语言实现了直接数字频率合成(DDS)技术。
In the way of system designing, we design and implement the digital baseband system by hardware description language in a FPGA system. 在系统设计方面，我们利用硬体描述语言研发数位基频系统，并且将系统实现在FPGA上。
This project only utilizes Hardware Description Language to describe the function of system.With the help of EDA tool, we can get the final design. 摘要该数字频率计的设计仅利用硬件描述语言来完成对系统功能的描述，在EDA工具的帮助下就可以得到最后的设计结果。
An IP core of 8051_MicroControl Unit has been designed and implemented using VHDL (VHSIC Hardware Description Language) in this thesis. 本文使用VHDL硬件描述语言，设计并实现了一个8051微控制器的IP核。
This thesis is to describe the design of a high reliability Fault-Tolerant controller utilizing the Hardware Description Language(HDL). 摘要:本论文以硬体描述语言为基础，设计一组高可靠度的容错控制器架构。
As a new try of SOC study and design methods, we have built high abstraction level models for CMOS current steering DACs, to simulate and predict the performance of DAC with math tool Matlab and advanced hardware description language Verilog-AMS. 作为SOC研究和设计方法的尝试，我们为COMS电流舵DAC建立了高层次模型，并运用数学工具Matlab和高级硬件描述语言Verilog-AMS来仿真和预测DAC的性能，进而指导DAC的设计。
The design method of traffic light control system by using Very-High-Speed Integrated Circuit Hardware Description Language(VHDL) is introduced,and the downloading of the controller design to the FPGA/CPLD chip in MAX+PLUS II is fulfilled. 用VHDL语言设计交通灯控制系统,并在MAX+PLUSII系统对FPGA/CPLD芯片进行下载,由于生成的是集成化的数字电路,没有传统设计中的接线问题,所以故障率低、可靠性高,而且体积小。
The study which is based on the new hardware description language and adapts the design method of ASIC will realize the advanced design of calculargraph whose accuracy will be 1/100s. 本项研究将基于新一代硬件描述语言(HDL)、采取ASIC(专用集成电路)设计方法,实现1/100s计时器的前端设计。
The RTL (Register Transfer Level)design is accomplished by Veirlog hardware description language, and synthesized with the standard cell library of SMIC 0.18um. The working frequency of the adaptive filter is 50MHz. 本设计采用Verilog 硬件描述语言完成系统的RTL(Register Transfer Level)级设计;选用SMIC 0.;18um 标准单元库完成逻辑综合;系统工作速度为50MHz。
Abstract: This paper presents a lantern automatic control program, and introduced the use of EDA technologies. VHDL hardware description language program to realize the system design. 摘要:本文提出了一个彩灯自动控制方案,并介绍了用EDA技术。VHDL硬件描述语言实现该方案的系统设计。
Issues concerning VHDL (VHSIC Hardware Description Language) programming, internal function modular description, encryption results and performance analysis of the encryption chip are reported. 对于这两种方案，文中给出了VHDL(硬件描述语言)编程、FPGA片内功能模块设计、加密效果以及硬件性能分析等。
The new system that uses the hardware description language (VHDL) and top-down methods can realize the function of logical control, including interface"s control of SDRAM, ROM, MCU and LCD. 该系统自带控制器,采用“微处理器+存储器+可编程逻辑器件“的模式进行设计,器件的功能均可用编程的方法实现;
Chapter tow introduced the conception of IP,the development and characteristic of popular HDL(Hardware Description Language)and coding style of several hardware descriptions. 第二章介绍了IP的概念以及几种流行的硬件描述语言的发展、特点，几种常见的硬件描述语言编码风格，也介绍了与IP软核开发有关的若干关键技术、两种主要EDA工具。