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- 全数字锁相环路DPLLdigital phase locked loop
- 全数字锁相环路all-digitized phase lock loop
- 一种大频偏和低信噪比条件下的全数字锁相环设计The Design of DPLL for Low SNR Signals with Large Frequency Offset
- 传统的数字锁相环 (DPLL)多采用吞脉冲的方法来实现DCO ,此方法要求工作频率远高于DPLL的输出频率。The normal idea to make up a digital controled oscillator (DCO)of the digital phase locked loop (DPLL)is to delete the pulses unwanted It need that the master clock frequency must be more faster than the output frepuency of the DPLL.
- 延迟锁相环路delay PLL
- 全数字网all-digital network
- 频率捷变脉冲雷达用快速捕获锁相环路Fast Acquisition Phas-Locked Loops for Frequency Agile Pulsed Radar Systems
- 全数字调速all digital speed-regulation
- 数字锁频环digital frequency lock loop(DFLL)
- 全数字仿算all-digital simulation
- 脉冲无线电通信系统的正交锁相环路同步方法Timing Acquisition of Impulse Radio System with Orthogonal Analog Phase Lock Loop
- 全数字超声digital imaging system
- 全数字调制器all - digital modulator
- 一个概周期锁相环路方程的概周期解的一个概周期锁相环路方程的概周期解的Existence, Uniqueness and Asymptotic Stability of Existence, Uniqueness and Asymptotic Stability of in Phase Locked Technology
- 全数字解调器all-digital demodulator
- 全数字测深仪all-digital depth sounder
- 本文首先介绍了该频率源的设计背景及电路方案,然后介绍了锁相环路、电调谐介质谐振器稳频振荡器(Vt-DRO)的设计过程。First, this paper introduces the background and block diagram of this frequency source, and then introduces the scheme of the sub-harmonic sampling phase-lock loop and push-push DRO.
- 全数字全息术all-digital holography
- 全数字应答机full digital answering machine
